Metadata-Version: 2.2
Name: zuspec-be-sw
Version: 0.0.9.13275747818rc0
Summary: Backend library to generate software output
Home-page: https://github.com/zuspec/zuspec-be-sw
Author: Matthew Ballance
Author-email: matt.ballance@gmail.com
License: Apache 2.0
Keywords: SystemVerilog,Verilog,RTL,Python
License-File: LICENSE
Requires-Dist: ciostream
Requires-Dist: zuspec-arl-dm>=0.0.9
Requires-Dist: vsc-dm
Requires-Dist: debug-mgr
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  Provides features for mapping ARL models to software output
  
